When the issue of the mandatory move to lead-free was first discussed in the electronics industry, it was the general consensus that the move would enable more reliable solder joints. Indeed, this was backed up by testing of tin-silver-copper systems, which highlighted that the trend should deliver stronger joints. However, as the research effort increases, it has become clear that at least with certain package types, lead-free assemblies could be more vulnerable to failures. In order to amend this problem, it is first necessary to thoroughly research the reasons for joint failure, incorporating issues such as reflow and cooling profiles, solder paste characteristics and stencil design.

Research carried out by the electronics group of Henkel revealed that lead-free solder joints in area array components are more vulnerable to failures due to mismatches in the CTE (coefficient of thermal expansion). Reasons for this include the lower ductility of the lead-free alloys along with the increased possibility of assembly warpage due to the higher peak reflow temperatures. In addition, the situation is likely to intensify as the industry moves towards finer pitched devices and thinner substrates.

Despite some exceptions – in the form of some devices such as SOICs and QFPs – chip type components are inclined to exhibit fractures in the joint on one side of the component after only 2,000 thermal shock cycles. At the wafer level, these effects are less easily observed or understood. For example, direct-attach Chip Scale Packages that encompass a large area and experience broad temperature fluctuations during normal use exhibit a reduced lead-free joint reliability.

As CSP devices continue the drive towards miniaturization with increasing numbers of interconnects, finer pitches and smaller solder ball diameters, the solder joint area and relational standoff will only exacerbate the effects of CTE mismatches. In addition, with CSPs proving ideal for various portable devices, the likelihood of drop vibration and stress, increases the need for comprehensive joint reliability.

Research has indicated that the use of underfills will help deliver the necessary levels of reliability for lead-free CSP devices. The use of this technique ensures that stress is distributed across the entire surface of the substrate, diminishing the possibility of failure due to concentrated stress. So, although CSPs were designed to be underfill-free assemblies, the move to lead-free manufacturing and the resulting brittleness of the solder joints particularly in area array packages has made underfilling these devices the most cost-effective and viable solution for enhancing reliability.

Despite this evidence, it is imperative that electronics assemblers select the materials that are optimized for their lead-free operations. For example, while some underfills are designed to withstand elevated lead-free temperatures, in the case of no-flow underfills, a dedicated lead-free formula is required. Ultimately, customers do not and should not accept a trade-off in terms of solder joint reliability against increased functionality, lead-free performance and miniaturization. While it is always beneficial to research areas such as CSP vulnerability more fully, it is clear that underfill materials are set to play a vital role in lead-free solder joint reliability in certain critical package types.